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NXP Semiconductors /MIMXRT1064 /LCDIF /VDCTRL3

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Interpret as VDCTRL3

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0VERTICAL_WAIT_CNT0HORIZONTAL_WAIT_CNT0 (VSYNC_ONLY)VSYNC_ONLY 0 (MUX_SYNC_SIGNALS)MUX_SYNC_SIGNALS

Description

LCDIF VSYNC Mode and Dotclk Mode Control Register3

Fields

VERTICAL_WAIT_CNT

In the VSYNC interface mode, wait for this number of DISPLAY CLOCK (pix_clk) cycles from the falling VSYNC edge (or rising if VSYNC_POL is 1) before starting LCD transactions and is applicable only if WAIT_FOR_VSYNC_EDGE is set
HORIZONTAL_WAIT_CNT

In the DOTCLK mode, wait for this number of clocks from falling edge (or rising if HSYNC_POL is 1) of HSYNC signal to account for horizontal back porch plus the number of DOTCLKs before the moving picture information begins
VSYNC_ONLY

This bit must be set to 1 in the VSYNC mode of operation, and 0 in the DOTCLK mode of operation.
MUX_SYNC_SIGNALS

When this bit is set, the LCDIF block will internally mux HSYNC with LCD_D14, DOTCLK with LCD_D13 and ENABLE with LCD_D12, otherwise these signals will go out on separate pins

Links

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Register License

Copyright 2016-2019 NXP All rights reserved.

SPDX-License-Identifier: BSD-3-Clause

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data